2020 차세대 리소그래피 학술대회

2020 Next Generation Lithography Conference
Nov. 18~19, 2020

Online Conference

Plenary Speakers
Plenary Talk 1
Atomic Scale Patterning: how EUV can get us there

Dr. Patrick Naulleau (Director, CXRO at LBNL)

Extreme Ultraviolet Lithography (EUVL) has DUV immersion lithography in high volume production at the leading-edge node and 5-nm EUV devices will soon be available. After 35 years of development, 2019 marked the year where chips fabricated using EUV lithography first became commercially available. Despite this tremendous achievement, much work remains to be done to ensure the extendibility of the technology which depends on the development of high NA (NA ≥ 0.5) systems and processes. High NA significantly stresses several current challenges and brings with it fundamentally new challenges. The most significant new challenge arises from angular bandwidth limitations of the mask multilayer requiring the use of anamorphic optics, or new multilayer material systems as well as polarization concerns that have never been an issue before for EUV owing to the relatively small angles involved. The most significant existing challenge being pushed to a fundamentally new regime with high NA revolves around stochastics in photoresist materials and exposure processes. As we approach the atomic scale, the quantized nature of light and materials is becoming a very significant effect in ultimate performance of the process. Addressing these challenges will require the understanding and control of materials and their interaction with EUV photons at the atomic scale. In this presentation, I will highlight these challenges and explore modern material science techniques that may be brought to bear to address these challenges.
Biography

Patrick Naulleau received his B.S. and M.S. degrees in electrical engineering from the Rochester Institute of Technology, Rochester, NY, in 1991 and 1993, respectively. He received his Ph.D. in electrical engineering from the University of Michigan, Ann Arbor in 1997 specializing in optical signal processing and coherence theory. In 1997 Dr. Naulleau joined Berkeley Lab on the EUV LLC program building the world’s first EUV scanner. From June 2005 through March 2008, Dr. Naulleau additionally joined the faculty at the University at Albany, SUNY as Associate Professor, also concentrating in the area of EUV lithography. In April 2010 Dr. Naulleau took the position of Director of the Center for X-ray Optic at Lawrence Berkeley National Laboratory. Dr. Naulleau has over 350 publications as well as 19 Patents and is a Fellow of OSA and SPIE.
Plenary Talk 2
Memory Technology 2020 and Beyond

Dr. Jeongdong Choe (Senior Technical Fellow, TechInsights)

DRAM cell scaling down to 16 nm design rule (D/R) or beyond has already been productized from major DRAM players such as Samsung, Micron and SK Hynix. They’re developing n+1 and n+2 generations so called 1a (or 1α) and 1b (or 1β) now, which means DRAM cell D/R might be able to further scale down to sub-12 nm with/without EUV adoption for DRAM cell patterning. The cell design scaling down is getting slower due to many scaling issues including patterning, leakage and sensing margin. Graphic DRAM and high bandwidth memories such as GDDR6, HBM2 and HMC2 adopted 20 nm or 10 nm-class DRAM technology nodes. Camera modules on smartphones have a triple-die structure by adding a low power DRAM die into the module. Some innovations such as higher-k dielectric materials, pillar capacitor and recess channel LV transistors can be seen in the advanced DRAM cell design.

Major NAND manufacturers are on the race to increase the number of vertical 3D NAND gates, they all have already introduced their own 9xL 3D NAND devices. Samsung 92L V-NAND (V5), KIOXIA and Western Digital Company (WDC) 96L BiCS4, Intel/Micron 96L FG CuA, and SK Hynix 96L 4D NAND PUC products are on the market. Many innovative changes are upcoming. Beyond storage density, 3D NAND is used for the fastest SSDs, such as Samsung’s Z-SSD. Total number of vertical gates stacked is already over one hundred, for example, KIOXIA’s 109 gates and SK Hynix’ 115 gates for their 96L 3D NAND products. Bit Density reached up to 9.0 Gb/mm2 with QLC NAND design.

Intel extends XPoint memory application not only for conventional SSD but also DCPMM persistent memory, although Micron’s QuantX has been delayed. Everspin’s 3rd generation STT-MRAM (pMTJ) and Adesto’s 2nd generation ReRAM (CBRAM) technologies are on the market.

We’ll discuss current and future DRAM, NAND and Emerging memory technology including process, design, and materials.
Biography

Dr. Jeongdong Choe is a Senior Technical Fellow at TechInsights. He has over 28 years of experience in the semiconductor industry, R&D and reverse engineering on DRAM, NAND/NOR FLASH, SRAM/Logic and emerging memory products such as MRAM, PCRAM, XPoint, ReRAM and FeRAM. He worked for SK Hynix and Samsung Electronics for over 20 years. He joined TechInsights and has been focusing on technology analysis on semiconductor process, device and architecture design. He has written many articles on memory technology including memory technology trend and roadmaps.
Plenary Talk 3
Beyond COV19-Challenges and Opportunities of Displays

Dr. Gyoowan Han (Master, Samsung Display)

Even though there have been a lot of activities in the virtual world before, the non-face-to-face virtual activities jumped tremendously on the Internet 5G era due to COVID-19, in conjugation with non-face-to-face culture, and this brings opportunities as well as challenges to the display business. While the need for visual information on the screens brought traditional displays on the market, the need for visual interaction has brought the surge in digitalization. Various technological developments are under the way for visual interaction. This session will introduce new directions in this field, new technical achievements and approaches in the display industry.
Biography

Educational Background
· Ph.D in Electro Optics at University of Dayton, Ohio
· MS in Physics at University of Dayton, Ohio
· BS in Physics Soongsil University

Professional Background
· 2012.07 ~ Present : Master, Mechatronics Tech. Center (Samsung Display)
· 2008.09 ~ 2012.07 : Samsung SMD, Manufacturing Tech. Team
· 2000.03 ~ 2008.09 : Samsung SDI, Advanced Engineering Center